AD9171 Dual, 16-Bit, 6.2 GSPS RF DAC with Single Channelizer

Product Details

The AD9171 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 6.2 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band direct to radio frequency (RF) wireless applications.

The AD9171 features one complex data input channels per RF DAC. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, frequency planning. The device supports up to a 516 MSPS complex data rate per input channel.

The AD9171 is available in a 144-ball BGA_ED package.

PRODUCT HIGHLIGHTS

  1. Supports one complex data input channel per RF DAC at a maximum complex input data rate of 513 MSPS with 12-bitresolution and 516 MSPS with 16-bit resolution options. There is one independent NCO per input channel.
  2. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.

APPLICATIONS

  • Wireless communications infrastructure
    • Single-band base station radios
  • Instrumentation, automatic test equipment (ATE)

Features and Benefits

  • Supports single-band wireless applications
    • 1 complex data input channel per RF DAC
    • 516 MSPS maximum complex input data rate per input channel
    • 1 independent NCO per input channel
  • Proprietary,  low spurious and distortion design
    • 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
    • SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output
  • Flexible 8-lane,  15.4 Gbps JESD204B interface
    • Supports single-band use cases
    • Supports 12-bit high density mode for increased data throughput
  • Multiple chip synchronization
    • Supports JESD204B Subclass 1
  • Selectable interpolation filter for a complete set of input data rates
    • 2×, 3×, 4×, and 6× configurable data channel interpolation
    • 6× and 8× configurable final interpolation
  • Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 3.1 GHz
  • Transmit enable function allows extra power saving and downstream circuitry protection
  • High performance, low noise PLL clock multiplier
    • Supports 6.2 GSPS DAC update rate
    • Observation ADC clock driver with selectable divide ratios
  • Low power
    • 1.45 W at 6 GSPS, single-channel mode
  • 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch